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1 of 1 6 features ? integrated nv sram, real - time clock, crystal, power - fail control circuit, and lithium energy source ? clock registers are accessed identically to the static ram. these registers are resident in the eight top ram locations. ? cent ury byte register (i.e., y2k compliant) ? totally nonvolatile with over 10 years of operation in the absence of power ? bcd - coded century, year, month, date, day, hours, minutes, and seconds with automatic leap - year compensation valid up to the year 2100 ? batte ry voltage - level indicator flag ? power - fail write protection allows for 10% v cc power - supply tolerance ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? dip module only standard jedec byte - wide 32k x 8 static ram pinout ? powercap module board only surface - mountable package for direct connection to powercap containing battery and crystal replaceable battery (powercap) power - on reset output pin - for - pin compatible with other densities of ds174xp tim ekeeping ram ? also available in industrial temperature range: - 40c to +85c ? ul recognized pin configurations 1 n.c. 2 3 n.c. n.c. rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n.c. a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 n.c. x1 gnd v bat x2 powercap module board (uses ds9034pcx+ or ds9034i - pcx + powercap) ds1744p top view v cc we a13 a8 a9 a11 oe a10 ce dq7 dq 6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ds1744 edip 19 - 5502; rev 3 /1 2 ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 2 of 16 pin description pin name function edip powercap 1 32 a14 address input 2 30 a12 3 25 a7 4 24 a6 5 23 a5 6 22 a4 7 21 a3 8 20 a2 9 19 a1 10 18 a0 21 28 a10 23 29 a11 24 27 a9 25 26 a8 26 31 a13 11 16 dq0 data input/output 12 15 dq1 13 14 dq2 15 13 dq3 16 12 dq4 17 11 dq5 18 10 dq6 19 9 dq7 14 17 gnd ground 20 8 ce active - low chip - enable input 22 7 oe active - low output - enable input 27 6 we active - low write - enable input 28 5 v cc power - supply input 4 rst active - low reset output, open drain. requires a pullup resistor for proper operation. 1, 2, 3, 33, 34 n. c. no connection x1, x2, v bat crystal connections, v bat battery connection
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 3 of 16 ordering information part voltage (v) temp range pin - package top mark** ds1744 - 70+ 5.0 0c to +70c 28 edip ds1744+70 ds1744 - 70ind + 5.0 - 40c to +85c 28 edip ds1744 + 70 ind ds1744w - 120+ 3.3 0c to +70c 28 edip ds1744w+120 ds1744w - 120ind + 3.3 - 40c to +85c 28 edip ds1744w + 120 ind ds1744p - 70+ 5.0 0c to +70c 34 powercap* ds1744p+70 ds1744p - 70ind + 5.0 - 40c to +85c 34 powercap* ds1744p + 70 ind ds1744wp - 120+ 3.3 0c to +70 c 34 powercap* ds1744wp+120 ds1744wp - 120ind + 3.3 - 40c to +85c 34 powercap* ds1744wp + 120 ind + denotes a lead (pb) - free/rohs - compliant package . * ds9034 - pcx + or ds9034i - pcx + required (must be ordered separately). ** a + anywhere in the top mark denote s a lead - free device. an ind denotes an industrial temperature grade device. description the ds1744 is a full - function, year - 2000- compliant (y2kc), real - time clock/calendar (rtc) and 32k x 8 nv sram. user access to all registers within the ds1744 is a ccomplished with a byte - wide interface as shown in figure 1. the rtc information and control bits reside in the eight uppermost ram locations. the rtc registers contain century, year, month, date, day, hours, minutes, and seconds data in 24 - hour bcd format . corrections for the date of each month and leap year are made automatically. the rtc clock registers are double - buffered to avoid access of incorrect data that can occur during clock update cycles. the double - buffered system also prevents time loss as th e timekeeping countdown continues unabated by access to time register data. the ds1744 also contains its own power - fail circuitry that deselects the device when the v cc supply is in an out - of - tolerance condition. this feature prevents loss of data from unp redictable system operation brought on by low v cc as errant access and update cycles are avoided.
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 4 of 16 figure 1. ds1744/ds1744p block diagram packages the ds1744 is available in two packages (28 - pin encapsulated dip and 34 - pin powercap module). the 28- p in edip module integrates the crystal, lithium energy source, and silicon all in one package. the 34 - pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design al lows the powercap to be mounted on top of the ds1744p after the completion of the surface - mount process. mounting the powercap after the surface - mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflo w. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shipped in separate containers. the part number for the powercap is ds9034pcx. clock operations reading the clock while the double - buf fered register structure reduces the chance of reading incorrect data, internal updates to the ds1744 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the internal clock register updating process does not affect clock accuracy. updating is halted when a 1 is written into the read bit, bit 6 of the century register (table 2). as long as a 1 remains in that position, updating is halted. after a halt is issued, the registers reflect the count , that is, day, date, and time that was current at the moment the halt command was issued. however, the internal clock registers of the double - buffered system continue to update so that the clock accuracy is not affected by the access of data. all the ds17 44 registers are updated simultaneously after the internal clock - register updating process has been re - enabled. updating is within a second after the read bit is written to 0. the read bit must be a 0 for a minimal of 500 s to ensure the external registers are updated. ds1744/ds1744p
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 5 of 16 table 1. truth table v cc ce oe we mode dq power v cc > v pf v ih x x deselect high - z standby v il x v il write data in active v il v il v ih read data out active v il v ih v ih read high - z active v so < v cc < v pf x x x deselect high - z cmos standb y v cc < v so < v pf x x x deselect high - z data - retention mode setting the clock as shown in table 2, bit 7 of the century register is the write bit. setting the write bit to a 1, like the read bit, halts updates to the ds1744 registers. the user can then load them with the correct day, date, and time data in 24 - hour bcd format. resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. stopping and starting the clock oscillator the clock oscillator can be stopped at any time. to increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb (bit 7) of the seconds registers (table 2). setting it to a 1 stops t he oscillator. frequency test bit as shown in table 2, bit 6 of the day byte is the frequency test bit. when the frequency test bit is set to logic 1 and the oscillator is running, the lsb of the seconds register toggles at 512hz. when the seconds registe r is being read, the dq0 line toggles at the 512hz frequency as long as conditions for access remain valid (i.e., ce low, oe low, we high, and address for seconds register remain valid and stab le). clock accuracy (dip module) the ds1744 is guaranteed to keep time accuracy to within 1 minute per month at +25 c. the rtc is calibrated at the factory by maxim using nonvolatile tuning elements, and does not require additional calibration. for this reason, methods of field clock calibration are not available and not necessary. clock accuracy is also affected by the electrical environment; caution should be taken to place the rtc in the lowest - level emi section of the pc board layout. for additional i nformation, refer to application note 58 : crystal considerations with maxim real - time clocks. clock accuracy (powercap module) the ds1744 and ds9034pcx are individually tested for accuracy. once mounted together, the module typically keeps time acc uracy to within 1.53 minutes per month (35ppm) at +25c. clock accuracy is also affected by the electrical environment and caution should be taken to place the rtc in the lowest - level emi section of the pc board layout. for additional information, refer t o application note 58: crystal considerations with maxim real - time clocks.
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 6 of 16 table 2. register map address data function range b7 b6 b5 b4 b3 b2 b1 b0 7fff 10 year year year 00 - 99 7ffe x x x 10 month month month 01-12 7ffd x x 10 date date date 01 - 31 7ffc bf ft x x x day day 01 - 07 7ffb x x 10 hour hour hour 00 - 23 7ffa x 10 minutes minutes minutes 00 - 59 7ff9 osc 10 seconds seconds seconds 00 - 59 7ff8 w r 10 century century century 00 - 39 osc = stop bit r = read bit ft = frequency test w = w rite bit x = see note bf = battery flag note: te t e ot e t t e et to te e to ee oe o oeto retrieving data from ram or clock the ds1744 is in the read mode whenever oe (output enable) is low, we (write enable) is high, and ce (chip enable) is low. the device architecture allows ripple - through access to any of the address locations in the nv sram. valid data is available at the dq pins within t aa after the last address input is stable, providing that the ce and oe access times and states are satisfied. if ce or oe access times and states are n ot met, valid data is available at the latter of chip - enable access (t cea ) or at output - enable access time (t oea ). the state of the dq pins is controlled by ce and oe . if the outputs are activated before t aa , the d ata lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, output data remains valid for output - data hold time (t oh ) but then goes indeterminate until t he next address access. writing data to ram or clock the ds1744 is in the write mode whenever we and ce are in their active state. the start of a write is referenced to the latter occurring transition of we or ce . the addresses must be held valid throughout the cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in mu st be valid t ds prior to the end of write and remain valid for t dh afterward. in a typical application, the oe signal is high during a write cycle. however, oe can be active provided that care is taken with the dat a bus to avoid bus contention. if oe is low prior to we transitioning low, the data bus can become active with read data defined by the address inputs. a low transition on we then disables the output t wez after we goes active.
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 7 of 16 data - retention mode the 5v device is fully accessible and data can be written or read only when v cc is greater than v pf . however, when v cc is below the power - fail point, v pf (point at which write prot ection occurs), the internal clock registers and sram are blocked from any access. at this time the power - fail reset - output signal ( rst ) is driven active and remains active until v cc returns to nominal levels. when v cc falls below the b attery switch point v so (battery supply level), device power is switched from the v cc pin to the backup battery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3v device is fully accessible, and d ata can be written or read only when v cc is greater than v pf . when v cc falls below v pf access to the device is inhibited. at this time the power - fail reset - output signal ( rst ) is driven active and remains active until v cc returns to nom inal levels. if v pf is less than v so , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than v so , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v so . rtc op eration and sram data are maintained from the battery until v cc is returned to nominal levels. the rst signal is an open - drain output and requires a pullup. except for the rst , all control, data, and address signals must be powered down when v cc is powered down. battery longevity the ds1744 has a lithium power source that is designed to provide energy for clock activity and clock and ram data retention when the v cc supply is not present. the capability of this intern al power supply is sufficient to power the ds1744 continuously for the life of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at +25 c with the internal clock oscillator running in the absence of v cc pow er. each ds1744 is shipped from maxim with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery - backup operation. actual life expe ctancy of the ds1744 is much longer than 10 years since no lithium battery energy is consumed when v cc is present. battery monitor the ds1744 constantly monitors the battery voltage of the internal battery. the battery flag bit (bit 7) of the day register is used to indicate the voltage - level range of the battery. this bit is not writable and should always be a 1 when read. if a 0 is ever present, an exhausted lithium energy source is indicated, and both the contents of the rtc and ram are questionable.
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 8 of 16 ab solute maximum ratings voltage range on any pin relative to ground 5.5v version .... ... - 0.3v to +6.0v 3.3v version ...- 0.3v to +4.6v storage tempe rature range edip.......................... .. ... - 40c to +85c powercap.................... . - 55c to +125c lead temperature (soldering, 10s) .. ................................................ ............... .. +260c note: edip is hand or wave - soldered only. soldering temperature (reflow, powercap)............................................................. .................................................... +260c this is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operation se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affec t reliability. operating range range temp range v cc commercial 0c to +70c, noncondensing 3.3v 10% or 5v 10% industrial - 40c to +85c, noncondesnsing 3.3v 10% or 5v 10% recommended dc operating conditions (t a = over the operating range) parameter s ymbol min typ max units notes logic 1 voltage (all inputs) v cc = 5v 10% v cc = 3.3v 10% v ih 2.2 v cc + 0.3v v 1 v ih 2.0 v cc + 0.3v v 1 logic 0 voltage (all inputs) v cc = 5v 10% v cc = 3.3v 10% v il - 0.3 0.8 v 1 v il - 0.3 0.6 v 1 dc electrical cha racteristics (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes active supply current i cc 75 ma 2, 3 , 10 ttl standby current ( ce = v ih ) i cc1 6 ma 2, 3 cmos standby current ( ce v cc - 0.2v) icc 2 4 ma 2, 3 input leakage current (any input) i il - 1 +1 a output leakage current (any output) i ol - 1 +1 a output logic 1 voltage (i out = - 1.0ma) v oh 2.4 1 output logic 0 voltage (i out = +2.1ma) v ol 0.4 1 write p rotection voltage v pf 4.25 4.50 v 1 battery switchover voltage v so v bat 1, 4
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 9 of 16 dc electrical characteristics ( v cc = 3.3v 10% , t a = over the operating range.) parameter symbol min typ max units notes active supply current i cc 30 ma 2, 3 , 10 ttl s tandby current ( ce = v ih ) i cc1 2 ma 2, 3 cmos standby current ( ce v cc - 0.2v) i cc2 2 ma 2, 3 input leakage current (any input) i il - 1 +1 a output leakage current (any output) i ol - 1 +1 a output logi c 1 voltage (i out = - 1.0ma) v oh 2.4 1 output logic 0 voltage (i out = +2.1ma) v ol 0.4 1 write protection voltage v pf 2.80 2.97 v 1 battery switchover voltage v so v bat or v pf v 1, 4 ac characteristics read cycle (5v) (v cc = 5.0v 10%, t a = ove r the operating range.) parameter symbol min typ max units notes read cycle time t rc 70 ns address access time t aa 70 ns ce to dq low - z t cel 5 ns ce access time t cea 70 ns ce data off time t cez 25 ns oe to dq low - z t oel 5 ns oe access time t oea 35 ns oe data off time t oez 25 ns output hold from address t oh 5 ns
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 10 of 16 ac characteristics read cycle (3. 3v) (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units notes read cycle time t rc 120 ns address access time t aa 120 ns ce to dq low - z t cel 5 ns ce access time t cea 120 ns ce data off time t cez 40 ns oe to dq low - z t oel 5 ns oe access time t oea 100 ns oe data off time t oez 35 ns output hold from address t oh 5 ns read cycle timing diagram
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 11 of 16 ac characteristics write cycle (5v) (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes write cycle time t wc 70 ns address setup time t as 0 ns we pulse w idth t wew 50 ns ce pulse width t cew 60 ns data setup time t ds 30 ns data hold time t dh1 0 ns 8 data hold time t dh2 0 ns 9 address hold time t ah1 5 ns 8 address hold time t ah2 5 ns 9 we data off time t wez 25 ns write recovery time t wr 5 ns ac characteristics write cycle (3.3v) (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units notes write cycle time t wc 120 ns address setup time t as 0 120 ns we pulse width t wew 100 ns ce pulse width t cew 110 ns ce and ce2 pulse width t cew 110 ns data setup time t ds 80 ns data hold time t dh1 0 ns 8 data hold time t dh2 0 ns 9 ad dress hold time t ah1 0 ns 8 address hold time t ah2 10 ns 9 we data off time t wez 40 ns write recovery time t wr 10 ns
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 12 of 16 write cycle timing diagram, write - enable controlled write cycle timing diagram, chip - enable cont rolled
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 13 of 16 power - up/down ac characteristics (5v) (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes ce or we at v ih before power - down t pd 0 s v cc fall time: v pf(m ax) to v pf(min) t f 300 s v cc fall time: v pf(min) to v so t fb 10 s v cc rise time: v pf(min) to v pf(max) t r 0 s power - up recover time t rec 35 ms expected data - retention time (oscillator on) t dr 10 years 5, 6 power - up/down timing (5v devi ce)
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 14 of 16 power - up/down characteristics (3.3v) (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units notes ce or we at v ih , before power - down t pd 0 s v cc fall time: v pf(max ) to v pf(min) t f 300 s v cc rise time: v pf(min) to v pf(max) t r 0 s v pf to rst high t rec 35 ms expected data - retention time (oscillator on) t dr 10 years 5, 6 power - up/down waveform timing (3.3v device) capacitance (t a = +25c) parameter symbol min typ max units notes capacitance on all input pins c in 14 pf capacitance on all output pins c o 10 pf
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 15 of 16 ac test conditions output load: 50pf + 1ttl gate input pulse levels: 0 to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) voltages are referenced to ground. 2) typical values are at +25 c and nominal supplies. 3) outputs are open. 4) battery switchover occurs at the lower of either the battery terminal v oltage or v pf . 5) data - retention time is at +25 c. 6) each ds1744 has a built - in switch that disconnects the lithium source until the user first applies v cc . the expected t dr is defined for dip modules and assembled powercap modules as a cumulative time in the a bsence of v cc starting from the time power is first applied by the user. 7) rtc modules (dip) can be successfully processed through conventional wave - soldering techniques as long as temperature exposure to the lithium energy source contained within does not e xceed +85 c. post - solder cleaning with water - washing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap: a. ) maxim recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (live - bug). b. ) hand soldering and touch - up: do not touch or apply the soldering iron to leads fo r more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad, and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to remove solder. 8) t ah1 , t dh1 are measured from we going high. 9) t ah2 , t dh2 are measured from ce going high. 10) t wc = 200ns. package information for the latest package outline information and land patte rns (footprints) , go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertai ns to the package regardless of rohs status. package type package code outline no. land pattern no. 28 edip mdf28+3 21 - 0245 34 pwrcp pc2+2 21 - 0246
ds1744/ds1744p y2k - compliant, nonvolatile timekeeping rams 16 of 16 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no cir cuit patent licenses are implied. maxim rese rves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 201 2 maxim integrated products maxim is a registered trademark of maxim integrated products. revision histor y revision date description pages changed 9/10 updated the ordering information table to include only lead - free parts; updated the absolute maximum ratings section to include the storage tem perature range and lead and soldering temperatures for edip and powercap packages; added note 1 0 to the i cc parameter in the dc electrical characteristics tables (for 5.0v and 3.3v) and the notes section; updated the package information table 3, 8, 9, 15 3/12 updated the absolute maximum ratings section to add the 5v and 3.3v voltage range 8

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